Temperature-Dependent Narrow Width Effects of 28-nm CMOS Transistors for Cold Electronics

We reported temperature-dependent narrow width effects on electrical characteristics of 28-nm CMOS transistors measured at temperature 77 K-300 K. At cryogenic temperatures, P-MOSFETs appear to have stronger temperature-induced threshold voltage ( $V_{\mathrm{ th}}$ ) increase and subthreshold swing SS reduction than N-MOSFETs, whereas the improvement in drain-induced barrier lowering (DIBL) is more evident N-MOSFETs. N-MOSFETs show typical reverse effect (RNWEs) terms roll-off along with rise-up narrowing channel-widths notation="LaTeX">$W_{\mathrm{ G}}$ ). In contrast, exhibit anomalous RNWE, that is, decreases (increases) decreasing from 3 notation="LaTeX">$\mu \text{m}$ 0.6 reversely increases (decreases) further 0.3 . RNWEs are clearly suppressed enhanced DIBL variations